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data sheet tle 6230 gp v2.3 page 18. nov. 2009 1 smart octal low-side switch features product summary ? short circuit protection ? overtemperature protection ? overvoltage protection ? 16 bit serial data input and diagnos- tic output (2 bit/ch. acc. spi protocol) ? direct parallel control of f our channels for pwm applications ? parallel inputs high or low active programmable ? general fault flag ? low quiescent current ? compatible with 3,3 v micro controllers ? e lecto s tatic d ischarge (esd) protection ? green product (rohs compliant) ? aec qualified application ? c compatible power switch for 12 v and 24v applications ? switch for automotive and industrial systems ? solenoids, relays and resistive loads ? robotic controls general description octal low-side switch in smart power technology (spt) with a s erial p eripheral i nterface (spi) and eight open drain dmos output stages. the tle 6230 gp is protected by embedded protection func- tions and designed for automotive and industrial applications. the output stages are controlled via an spi interface. additionally four channels can be c ontrolled direct in paral lel for pwm applications. therefore the tle 6230 gp is particularly suit able for engine management and powertrain systems. reset fault cs output stage output control buffer serial interface spi logic sclk si 88 gnd vs so 1 4 in1 in2 in3 in4 out1 out8 prg v bb vs as ch. 1 as ch. 1 as ch. 1 16 gnd protection functions supply voltage v s 4.5 ? 5.5 v drain source clamping voltage v ds(az)max 55 v on resistance r on 0.75 ? output current (all outp.on equal) i d(nom) 500 ma (individually) 1 a pg-dso 36
data sheet tle 6230 gp v2.3 page 18. nov. 2009 2 block diagram detailed block diagram fault reset cs channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 channel 8 channel 1 in2 sclk vs in1 out1 out2 out3 out4 out5 out6 out7 out8 in3 in4 spi interface 16 bit normal function scb/overload open load short to ground & output stage prg vs gnd & & & si so gnd
data sheet tle 6230 gp v2.3 page 18. nov. 2009 3 pin description pin configuration (top view) pin symbol function 1 gnd ground 2 nc not connected 3 nc not connected 4 out1 power output channel 1 5 out2 power output channel 2 6 in1 input channel 1 7 in2 input channel 2 8 vs supply voltage 9 reset reset 10 cs chip select 11 prg program (inputs high or low-active) 12 in3 input channel 3 13 in4 input channel 4 14 out3 power output channel 3 15 out4 power output channel 4 16 nc not connected 17 nc not connected 18 gnd ground 19 gnd ground 20 nc not connected 21 nc not connected 22 out5 power output channel 5 23 out6 power output channel 6 24 nc not connected 25 nc not connected 26 fault general fault flag 27 so serial data output 28 sclk serial clock 29 si serial data input 30 nc not connected 31 nc not connected 32 out7 power output channel 7 33 out8 power output channel 8 34 nc not connected 35 nc not connected 36 gnd ground heat slug internally connected to ground pins gnd 1 ? 36 gnd nc 2 35 nc nc 3 34 nc out1 4 33 out8 out2 5 32 out7 in1 6 31 nc in2 7 30 nc vs 8 29 si reset 9 28 sclk cs 10 27 so prg 11 26 fault in3 12 25 nc in4 13 24 nc out3 14 23 out6 out4 15 22 out5 nc 16 21 nc nc 17 20 nc gnd 18 19 gnd power so 36
data sheet tle 6230 gp v2.3 page 18. nov. 2009 4 maximum ratings for t j = ? 40c to 150c parameter symbol values unit supply voltage v s -0.3 ... + 7 v continuous drain source voltage (out1...out8) v ds 40 v input voltage, all inputs and data lines v in - 0.3 ... + 7 v load dump protection v load dump = u p + u s ; u p =13.5 v with automotive relay load r l = 70 ? r i 1 ) =2 ? ; t d =400ms; in = low or high with r l = 24 ? ; r i =2 ? ; t d =400ms; in = high or low v load dump 2 ) 80 52 v operating temperature range storage temperature range t j t stg - 40 ... + 150 - 55 ... + 150 c output current per channel (see el. characteristics) i d(lim) i d(lim) min a output current per channel @ t a = 25c (all 8 channels on; mounted on pcb ) 3 ) i d 500 ma output clamping energy (single pulse) i d = 0.5 a e as 50 mj power dissipation (mounted on pcb) @ t a = 25c p tot 3.3 w e lectro s tatic d ischarge v oltage (human body model) according to mil std 883d, method 3015.7 and eos/esd assn. standard s5.1 ? 1993 output 1-8 pins all other pins v esd v esd 2000 2000 v v din humidity category, din 40 040 e iec climatic category, din iec 68-1 40/150/56 thermal resistance junction - case junction - ambient @ min. footprint junction - ambient @ 6 cm 2 cooling area with heat pipes r thjc r thja 5 50 38 k/w 1 ) r i =internal resistance of the load dump test pulse generator ld200 2 ) v loaddump is setup without dut connected to the generator per iso 7637-1 and din 40 839. 3 ) output current rating so long as maximum junction temperature is not exceeded. at t a = 125 c the output current has to be calculated using r thja according mounting conditions. pcb with heat pipes, backside 6 cm 2 cooling area minimum footprint
data sheet tle 6230 gp v2.3 page 18. nov. 2009 5 electrical characteristics parameter and conditions symbol values unit v s = 4.5 to 5.5 v ; t j = - 40 c to + 150 c ; reset = h (unless otherwise specified) min typ max 1. power supply, reset supply voltage 4 v s 4.5 -- 5.5 v supply current (outputs on) 5 i s(on) -- 1 2 ma supply current (outputs off) 5 i s(off) -- 1 2 ma minimum reset duration t reset,min 10 -- -- s 2. power outputs on resistance v s = 5 v ; i d = 500 ma t j = 25c t j = 150c r ds(on) -- -- 0.8 -- 1 1.7 ? output clamping voltage output off v ds(az) 40 -- 55 v current limit i d(lim) 1 1.5 2 a output leakage current v reset = l v bb =12v i d(lkg) -- -- 5 a turn-on time i d = 0.5 a, resistive load t on -- 8 12 s turn-off time i d = 0.5 a, resistive load t off -- 6 10 s 3. digital inputs input low voltage v inl - 0.3 -- 1.0 v input high voltage v inh 2.0 -- -- v input voltage hysteresis v inhys 50 100 200 mv input pull down/up current (in1 ... in4) i in(1..4) 20 50 100 a prg, reset pull up current i in(prg,res) 20 50 100 a input pull down current (si, sclk) i in(si,sclk) 10 20 50 a input pull up current ( cs ) i in(cs) 10 20 50 a 4. digital outputs (so, fault ) so high state output voltage i soh = 2 ma v soh v s - 0.4 -- -- v so low state output voltage i sol = 2.5 ma v sol -- -- 0.4 v output tri-state leakage current cs = h, 0 v so v s i solkg -10 0 10 a fault output low voltage i fault = 1.6 ma v faultl -- -- 0.4 v 4 for v s < 4.5v the power stages are switched according the input signals and data bits or are definitely switched off. this undervoltage reset gets active at v s = 3v (typ. value) and is guaranteed by design. 5 for reset = h.
data sheet tle 6230 gp v2.3 page 18. nov. 2009 6 electrical characteristics cont. parameter and conditions symbol values unit v s = 4.5 to 5.5 v ; t j = - 40 c to + 150 c ; reset = h (unless otherwise specified) min typ max 5. diagnostic functions open load detection voltage v ds(ol) v s -2.5 v s -2 v s -1.3 v output pull down current i pd(ol) 50 90 150 a fault delay time t d(fault) 50 100 200 s short to ground detection voltage v ds(shg) v s ?3.3 v s -2.9 v s -2.5 v short to ground detection current i shg -50 -100 -150 a current limitation; overload threshold current i d(lim) 1...8 1 1.5 2 a overtemperature shutdown threshold 6 hysteresis 6 t th(sd) t hys 170 -- -- 10 200 -- c k 6. spi-timing serial clock frequency (depending on so load) f sck dc -- 5 mhz serial clock period (1/fclk) t p(sck) 200 -- -- ns serial clock high time t sckh 50 -- -- ns serial clock low time t sckl 50 -- -- ns enable lead time (falling edge of cs to rising edge of clk ) t lead 250 -- -- ns enable lag time (falling edge of clk to rising edge of cs ) t lag 250 --- -- ns data setup time (required time si to falling of clk) t su 20 -- -- ns data hold time (falling edge of clk to si) t h 20 -- -- ns disable time @ c l = 50 pf 6 t dis -- -- 150 ns transfer delay time 7 ( cs high time between two accesses) t dt 200 -- -- ns data valid time c l = 50 pf 6 c l = 100 pf 6 c l = 220 pf 6 t valid -- -- -- 110 120 150 160 170 200 ns 6 this parameter will not be test ed but guaranteed by design 7 this time is necessary between two write accesses. to get the correct diagnostic information, the transfer delay time has to be extended to the maximum fault delay time t d(fault)max = 200s.
data sheet tle 6230 gp v2.3 page 18. nov. 2009 7 functional description the tle 6230 gp is an octal-low-side power switch which provides a serial peripheral inter- face (spi) to control the 8 power dmos switches, as well as diagnostic feedback. the power transistors are protected against short to v bb , overload, overtemperature and against over- voltage by an active zener clamp. the diagnostic logic recognizes a fault condition which can be read out via the serial diagnostic output (so). circuit description output stage control each output is independently controlled by an output latch and a common reset line, which disables all eight outputs. serial data input (si) is read on the falling edge of the serial clock. a logic high input data bit turns the respective output channel on, a logic low data bit turns it off. cs must be low whilst shifting all the serial data into the device. a low-to-high transition of cs transfers the serial data input bits to the output buffer. special conditions for channel 1 to 4: in addition to the serial control of the outputs it is possible to control channel 1 to channel 4 directly in parallel for pwm applications. these inputs are high or low active (programmable via prg pin) and anded with the spi control bit. the table shows the and-operation of the parallel input pin (here active high) and the corresponding spi bit. for an application where the parallel input is always "on", it is possibl e to switch the channel off via the spi bit, e.g. for diagnosis in off-state. ? spi priority for off-state operation with parallel inputs: set spi bits to logic high. operation via spi: connect parallel inputs to logic high (if programmed to active high). prg - program pin. prg = high ( v s ): parallel inputs channel 1 to 4 are high active prg = low (gnd): parallel inputs channel 1 to 4 are low active. if the parallel input pins are not connected (indep endent of high or low activity) it is guaranteed that the channels 1 to 4 are switched off. prg pin itself is internally pulled up when it is not connected. in 1 - 4 spi-bit 0 - 3 out 1 - 4 0 0 off 0 1 off 1 0 off 1 1 on
data sheet tle 6230 gp v2.3 page 18. nov. 2009 8 power transistor protection functions 8) each of the eight output stages has its own zener clamp, which causes a voltage limitation at the power transistor when solenoid loads are switched off. the outputs are provided with a current limitation set to a minimum of 1 a. the continuous current for each channel is 500 ma (all channels on). each output is protected by embedded protection functions. in the event of an overload or short to supply, the current is internally limited and the corresponding bit combination is set (early warning). if this operation leads to an overtemperature condition, a second protection level (about 170 c) will change the output into a low duty cycle pwm (selective thermal shut- down with restart) to prevent critical chip temperatures. spi signal description cs - chip select. the system microcontroller selects the tle 6230 gp by means of the cs pin. whenever the pin is in a logic low state, data can be transferred from the c and vice versa. cs high to low transition: - diagnostic status information is transferred from the power outputs into the shift register. - serial input data can be clocked in from then on - so changes from high impedance state to logic high or low state corresponding to the so bits cs low to high transition: - transfer of si bits from shift register into output buffers - reset of diagnosis register to avoid any false clocking the serial clock input pin sclk should be logic low state during high to low transition of cs . when cs is in a logic high state, any signals at the sclk and si pins are ignored and so is forced into a high impedance state. sclk - serial clock. the system clock pin clo cks the internal shift register of the tle 6230 gp. the serial input (si) accepts data into the input shift register on the falling edge of sclk while the serial output (so) shifts diagnostic information out of the shift register on the rising edge of serial clock. it is essential that the sclk pin is in a logic low state whenever chip select cs makes any transition. the number of clock pulses will be counted during a chip se- lect cycle. the received data w ill only be accepted, if exactl y 16 clock pulses were counted during cs is active. si - serial input. serial data bits are shifted in at this pin, the most significant bit first. si infor- mation is read in on the falling edge of sclk. input data is latched in the shift register and then transferred to the control buffer of the output stages. the input data consists of two bytes - a "control byte? followed by a "data byte". the control byte contains the information as to whether the data byte will be accepted or ignored (see di- agnostics section). the data byte contains the input information for the eight channels. a logic 8) the integrated protection functions prevent an ic destruction under fault conditions and may not be used in normal operation or perma- nently
data sheet tle 6230 gp v2.3 page 18. nov. 2009 9 high level at this pin (within the data byte) will switch on the power switch, provided that the corresponding parallel input is also switched on (and-operation for channel 1 to 4). so - serial output. diagnostic data bits are shifted out serially at this pin, the most significant bit first. so is in a high impedance state until the cs pin goes to a logic low state. new diag- nostic data will appear at the so pin following the rising edge of sclk. reset - reset pin. if the reset pin is in a logic low state, it clears the spi shift register and switches all outputs off. an internal pull-up structure is provided on chip. diagnostics fault - fault pin. there is a general fault pin (open drain) which shows a high to low transi- tion as soon as an error occurs for any one of the eight channels. this fault indication can be used to generate a c interrupt. therefore a ?diagnosis? interrupt routine need only be called after this fault indication. this saves processo r time compared to a cycl ic reading of the so information. as soon as a fault occurs, the fault information is latched into the diagnosis register. a new error will over-write the old error report. serial data out pin (so) is in a high impedance state when cs is high. if cs receives a low signal, all diagnosis bits can be shifted out serially. the rising edge of cs will reset all error registers. there are two diagnostic bits per channel configured as shown in figure 1. normal function: the bit combination hh indicates that there is no fault condition, i.e. normal function. overload, short circuit to battery (scb) or overtemperature: hl is set when the current limitation gets active, i.e. there is a overload, short to supply or overtemperature condition. open load: an open load condition is detected when the drain voltage decreases below 3 v (typ.). lh bit combination is set. short circuit to gnd: if a drain to ground short circuit exists and the drain to ground current exceeds 100 a, short to ground is detected and the ll bit combination is set. diagnostic serial data out so hh normal function hl overload, shorted load or overtemperature lh open load ll shorted to ground ch.8 ch.7 ch.6 ch.5 15 14 13 12 11 10 9 8 - - - - - figure 1: two bits per channel diagnostic feedback
data sheet tle 6230 gp v2.3 page 18. nov. 2009 10 a definite distinction between open load and short to ground is guaranteed by design. the standard way of obtaining diagnostic information is as follows: clock in serial information into si pin and wait approximately 150 s to allow the outputs toset- tle. clock in the identical serial information once again - during this process the data coming out at so contains the bit combinations representing the diagnosis conditions as described in figure 1. by means of the control byte it is possible either to: a) control the eight outputs according to the data byte, as well as being able to read the diagnostic information or b) purely get diagnostic information without changing the state of the outputs. a) serial control of outputs hhhhhhhh lhlhhlll control byte data byte 12 4 43 44 1 2 4 43 44 : serial input information control byte is set to ffhex: data byte will be accepted. the outputs will be switched on or off according to the information of the data byte and the parallel inputs (channel 1 to 4 be- cause of and operation). all other control words except the one for 'diagnosis only = 00hex' will also be accepted as a valid control word and the data will be accepted. example: hllhlhlh dddddddd: outputs will switch according to the data bits. b) diagnosis only llllllll xxxxxxxx control byte data byte 12 4 43 44 1 2 4 43 44 : serial input information control byte is set to 00hex: data byte will be ignored. diagnostic information can be read out at any time with no change of the switching conditions. only 00hex means 'diagnosis only'.
data sheet tle 6230 gp v2.3 page 18. nov. 2009 11 timing diagrams figure 2: serial interface figure 3: input timing diagram figure 4: so valid time waveforms enable and disable time waveforms c o n t r o l byte 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cs sclk si so msb lsb t lead t sckh 0.2v s t lag t h t sckl 0.2 v s t su 0.7v s 0.2v s cs sclk si 0.7v s 0.7vs t dt t valid sclk cs so t dis 0.2 v s so 0.7 v s 0.7 v s 0.2 v s so 0.7 v s 0.2 v s
data sheet tle 6230 gp v2.3 page 18. nov. 2009 12 figure 5: power outputs timing is valid for resistive load wi th parallel and serial control. rising edge of chip select initiates the switching application circuits t t t on t off 80% v ds v in 20% out1 out2 out8 tle 6230 gp si so clk cs vs v s = 5v reset gnd v bb clk mtsr mrst p xy c e.g. c167 in1 in2 in3 in4 prg fault 10k c
data sheet tle 6230 gp v2.3 page 18. nov. 2009 13 typical electrical characteristics drain-source on-resistance r ds(on) = f (t j ) ; v s = 5v output clamping voltage v ds(az) = f (t j ) ; v s = 5v figure 6 : typical on resistance versus junction-temperature channel 1-8 figure 7 : typical clamp voltage versus junction-temperature channel 1-8 typical clamping voltage 41 42 43 44 45 -50 -25 0 25 50 75 100 125 150 175 tj[c] vds(az) [v] channel 1-8 typical drain- source on-resistance 0,4 0,5 0,6 0,7 0,8 0,9 1 1,1 1,2 1,3 1,4 1,5 -50 -25 0 25 50 75 100 125 150 175 tj[c] rds(on) [ohm ] channel 1-8
data sheet tle 6230 gp v2.3 page 18. nov. 2009 14 maximum single clamp energy parallel spi configuration engine management application tle 6230 gp in combination with tle 6240 gp (16-fold switch) for relays and general purpose loads and tle 6220 gp (quad switch) to drive the injector valves. this arrange- ment covers the numerous loads to be driven in a modern engine manage- ment/powertrain system. from 28 channels in sum 16 can be controlled direct in parallel for pwm applications. 4 si clk so 4 si clk so cs cs mtsr mr st clk p x.y p x.1-4 p x.y p x.1-4 c c167 4 pwm channels 4 pwm channels cs injec tor 1 injec tor 2 injec tor 3 injec tor 4 tle 6220 gp quad tle 6230 gp octal 8 si clk so cs 8 pwm channels tle 6240 gp 16-fold p x.y p x.1-8 0 50 100 150 200 250 300 0 0,2 0,4 0,6 0,8 1 1,2 1,4 peak current [a] tle 6230, single clamp, linear current ramp maximum energy rating @ tj=150c figure 8 : maximum clamp energy (single event) versus peak current channel 1-8
data sheet tle 6230 gp v2.3 page 18. nov. 2009 15 package and ordering code (all dimensions in mm) pg-dso 36 tle 6230 gp
data sheet tle 6230 gp v2.3 page 18. nov. 2009 16 edition 2008-04-17 published by infineon technologies ag 81726 munich, germany ? 2008 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteris- tics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the applic ation of the device, infi neon technologies hereby disclaims any and all warranties and liabili- ties of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest in- fineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may cont ain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life -support devices or systems only with the ex- press written approval of infineon technologies, if a failure of such components can reasonably be ex- pected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to as- sume that the health of the user or other persons may be endangered.

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